1. Field of Invention
The present invention relates to a hydrofluoric acid (HF) vapor treatment process. More particularly, the present invention relates to a vapor treatment process that is capable of reducing oxide depletion.
2. Description of Related Art
Metal-oxide-semiconductor (MOS) transistors are one of the basic electronic devices in very large scale integration (VLSI) circuits. In general, a MOS transistor is made by forming an isolating region above a substrate, and then forming a stack of layers composed of various materials above the substrate. The most commonly used materials for forming the stack include silicon nitride/tungsten silicide/polysilicon/silicon dioxide (SiN/WSi/Polysilicon/SiO.sub.2). Next, using a patterned photoresist layer as a mask, the stack is etched to form a gate structure of a MOS transistor in the device area.
When the stack is etched to form the gate structure, a layer of polymer will also be formed around the gate terminal as a side reaction. In general, the polymer layer has to be removed using a hydrogen fluoride vapor etching method. However, the same hydrogen fluoride vapor for etching away the deposited polymer will also act on the protective oxide layer formed over the substrate for preventing damages by subsequent ion implantation. Consequently, using the conventional method to remove polymer deposit in a production line will lead to oxide depletion, and will result in low wafer yield.
FIG. 1A is a diagram showing the flow of wafers through a conventional vapor processing station for removing residual polymeric material around gate terminal structures.
First, as shown in FIG. 1A, a wafer 100 having residual polymeric material surrounding its gate structures is placed on the loader 102 of a processing station. Next, the wafer 100 is moved to the vapor process chamber 104 (VPC). Inside the vapor process chamber 104, hydrogen fluoride vapor reacts with the residual polymer. When the residual polymer is removed, the wafer 100 is transferred to the dry task chamber 106 (DTC) where the wafer 100 is cleaned with de-ionized water (DIW) to remove any residual gases on the wafer surface.
Finally, the wafer 100 is transferred from the DTC 106 to the unloader 108, and then the processed wafer 100 is transferred back to the production line from the unloader 108 for subsequent operations. Meanwhile, wafers 111, 122 and 133 are also fed to the processing station one by one and pass through various stages inside the processing station as indicated in FIG. 1A.
FIG. 1B is a diagram showing timing relation of various stages inside the vapor process chamber of a conventional processing station for clearing residual polymer around the gate structure of a wafer. In FIG. 1B, the vertical axis indicates the rotating speed (in rpm) of the wafer stand and the horizontal axis indicates the time (in seconds) inside the vapor process chamber. Furthermore, stages for carrying out each processing operation and the treatment within each time slot are also indicated.
The wafer 122 within the vapor process chamber 104 actually passes through three stages. In stage 1, gaseous nitrogen having a flow rate of about 20 liters per second (l/s) is passed into the vapor process chamber, and the operation is maintained for about 20 seconds. Next, in stage 2, gaseous hydrogen fluoride carried by gaseous nitrogen with a flow rate also of about 20 (l/s) is passed continuously for about 15 second. Finally, in stage 3, gaseous nitrogen having a flow rate of about 20 (l/s) is again passed into the vapor process chamber continuously for about 30 seconds so that residual gaseous hydrogen fluoride within the chamber is purged. Therefore, the total time spent in processing within the vapor process chamber 104 is about 67 seconds.
After the processing treatment within the vapor process chamber 104, the wafer is transferred to the dry task chamber 106, where the wafer is cleaned and dried.
FIG. 1C is a diagram showing the timing relation of various stages inside the dry task chamber of a conventional processing station for clearing residual polymer around the gate structure of a wafer. In FIG. 1C, the vertical axis indicates the rotating speed (in rpm) of the wafer stand and the horizontal axis indicates the time (in seconds) inside the dry task chamber. Furthermore, stages for carrying out each processing operation and the treatment within each time slot are also labeled.
Inside the dry task chamber 106, the wafer stand at first spins at about 500 rpm while de-ionized water (DIW) is sprayed on the top and backs surfaces of the wafer for about 25 seconds to remove any residual gases. Next, the wafer stand slows down to about 50 rpm, and then de-ionized water is again sprayed for another 5 seconds.
Thereafter, the wafer stand speeds up to around 2000 rpm and maintains that speed for about 60 seconds to carry out a spin/dry (S/D) operation. Due to high centrifugal force created by rapid spinning, the surfaces of wafer 111 are dried. Finally, the spinning wafer stand is allowed to stop within about 3 seconds. Hence, the total time spent within the dry task chamber 106 is about 101 seconds.
In a conventional processing station for removing residual polymer around a gate structure of a wafer, the wafer remains in the vapor process chamber (VPC) for a period of about 67 seconds, while the wafer has to remain in the dry task chamber (DTC) for a period of about 101 seconds.
Therefore, for a continuous flow system as shown in FIG. 1A, when the wafer 111 in the DTC 106 finishes processing, the wafer 122 in the VPC 104 has already finished all its required operations and has been left waiting for about 34 seconds. Since the following wafer 122 has to sit idle in the VPC 104 for about 34 seconds, any residual hydrogen fluoride in the chamber will continue its etch on oxide material and result in oxide depletion.
FIG. 1D is a diagram showing gate oxide material depletion versus slots on a piece of wafer after hydrogen fluoride vapor etching operation in a processing station.
In FIG. 1D, the vertical axis indicates thickness of the gate oxide material wasted in the vapor etching process and the horizontal axis indicates various slots on the wafer. For the aforementioned conventional method, a gate oxide thickness of between 6.02-12.17 .ANG. is lost. With a thick layer of gate oxide material removed, subsequent ion implantation operations can result in considerable damages to the substrate surface.
In light of the foregoing, there is a need to provide a method of reducing gate oxide depletion.